FTM3_OUTSEL=0, FTM2CH1SEL=0, FTM3SYNCBIT=0, FTM1SYNCBIT=0, FTM2CH0SEL=00, FTM0SYNCBIT=0, FTM1CH0SEL=00, FTM2SYNCBIT=0, FTM0_OUTSEL=0
FTM Option Register 1
FTM0SYNCBIT | FTM0 Sync Bit 0 (0): No effect. 1 (1): Write 1 to assert the TRIG1 input to FTM0. Software must clear this bit to allow other trigger sources to assert. |
FTM1SYNCBIT | FTM1 Sync Bit 0 (0): No effect. 1 (1): Write 1 to assert the TRIG1 input to FTM1. Software must clear this bit to allow other trigger sources to assert. |
FTM2SYNCBIT | FTM2 Sync Bit 0 (0): No effect. 1 (1): Write 1 to assert the TRIG1 input to FTM2. Software must clear this bit to allow other trigger sources to assert. |
FTM3SYNCBIT | FTM3 Sync Bit 0 (0): No effect. 1 (1): Write 1 to assert the TRIG1 input to FTM3. Software must clear this bit to allow other trigger sources to assert. |
FTM1CH0SEL | FTM1 CH0 Select 0 (00): FTM1_CH0 input 1 (01): CMP0 output 2 (10): CMP1 output 3 (11): CMP2 output |
FTM2CH0SEL | FTM2 CH0 Select 0 (00): FTM2_CH0 input 1 (01): CMP0 output 2 (10): CMP1 output 3 (11): CMP1 output |
FTM2CH1SEL | FTM2 CH1 Select 0 (0): FTM2_CH1 input 1 (1): exclusive OR of FTM2_CH0,FTM2_CH1, and FTM1_CH1 |
FTM0_OUTSEL | FTM0 channel modulation select with FTM1_CH1 0 (0): No modulation with FTM1_CH1 1 (1): Modulation with FTM1_CH1 |
FTM3_OUTSEL | FTM3 channel modulation select with FTM2_CH1 0 (0): No modulation with FTM2_CH1 1 (1): Modulation with FTM2_CH1 |